Semiconductor devices such as logic and memory devices are typically fabricated by a sequence of processing steps applied to a substrate or wafer. The various features and multiple structural levels of the semiconductor devices are formed by these processing steps. For example, lithography is a semiconductor fabrication process that involves generating a pattern on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated on a single semiconductor wafer and then separated into individual semiconductor devices.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield. As design rules and process windows continue to shrink in size, inspection systems are required to capture a wider range of physical defects on wafer surfaces while maintaining high throughput.
Wafer manufacturing process control is typically performed based on low wafer sampling using a slow, but sensitive, inspection tool, followed by review using a scanning electron microscope (SEM). In other cases, process monitoring and control is achieved by way of a learning-based method where a process engineer learns how long the process tool can be used before requiring maintenance. This process engineer-based approach is prone to random failures because there is no in-line feedback or older automated classifiers. In both of these previous techniques, there is no early detection of process tool issues. Issues are only detected once a process tool has become problematic and creates defects that can be observed on inspection. Additionally, these techniques are slow, and, therefore, wafer sampling is low. Such techniques create large overhead, such as for process tools that have a one or two day preventative maintenance cycle. These techniques also can cause reduced yield, which negatively impacts foundries that may only have a few lots per device to manufacture. Furthermore, normal class may be more common on inspected wafers, which makes detection difficult. Outliers typically are infrequent and may manifest themselves in unexpected combinations.
In practice, semiconductor processes are typically subject to multiple parameters that may have interdependence among each other. Hence, for effective process optimization, it is necessary to identify which parameters are the most significant in determining the yield of a process, and then to determine the optimal range of values (or “process window”) for each parameter. Furthermore, it is desirable to make this determination as early as possible in the semiconductor manufacturing process.
Critical dimensions in semiconductor manufacturing keep shrinking as 14 nm and 7 nm microarchitecture become more prevalent. However, the resolution capability is still λ/NA, where λ is imaging wavelength and NA is numerical aperture. To achieve higher resolution either λ is reduced or numerical aperture (NA) is increased. Extreme ultraviolet (EUV) lithography has been suggested to reduce the wavelength, but its economic viability has yet to be achieved. Therefore, lenses with high NA are used for better imaging, resulting in reduced depth of focus (DOF) as DOF is inversely proportional to NA2. Consequently, semiconductor manufacturing is much more sensitive to process variation. This impacts the yield since systematic patterning defects increase as a result of higher sensitivity to focus and dose. Even though scanner precision in controlling the process window is improving, other process constraints can affect focus and exposure. Therefore, a market for real-time technology for monitoring process window on production wafers exists. In other words, process window in a lithographic process is a collection of acceptable range foci and exposures that result in electronics circuits to be manufactured with desired specifications.
In current semiconductor fabrication techniques, a process window is optimized for only one parameter at a time, and the tradeoff between results of variations are not well accounted for. For example, if a critical dimension process window is optimized, this will require a shift in the oxide thickness process window. However, if the oxide thickness process window is to be optimized, the critical dimension process window will then shift. This can adversely affect the overall production yield.
Technologies for process window monitoring tend to monitor the tool performance and its stability, and, thus, catch process variation. However, these technologies cannot detect process fluctuations on product wafers due to the impact of other processes.
Accordingly, there is a need for high-throughput process monitoring and control that is capable of detecting non-compliance based on previously unknown patterns.